Renesas has chosen the AndesCore IP 32-bit RISC-V CPU cores to embed into ASSPs that will begin customer sampling in the second half of 2021.

“Renesas and Andes share the same vision to welcome the era of RISC-V being the mainstream CPU instruction set architecture (ISA for SoCs,” says  Frankwell Lin, President of Andes, “it marks the arrival of the open-source RISC-V ISA as a mainstream computing engine.”

News source : https://www.electronicsweekly.com/news/business/renesas-use-risc-v-cores-assps-2020-10/